1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a data driving apparatus and method for a liquid crystal display device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for capable of reducing the number of data driving integrated circuits and preventing a distortion of pixel signals.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device controls light transmittance of liquid crystal having a dielectric anisotropy using an electric field to display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix form, and a driving circuit for driving the liquid crystal display panel.
More specifically, as shown in FIG. 1, the liquid crystal display panel includes a liquid crystal display panel 2 having a plurality of pixel matrices, a gate driver 4 for driving a plurality of gate lines G10 to GLn of the liquid crystal panel 2, a data driver 6 for driving a plurality of data lines DL1 to DLm of the liquid crystal panel 2, a timing controller 8 for controlling driving timing of the gate driver 4 and the data driver 6 and a reference gamma voltage part 10 for supplying a reference gamma voltage to the data driver 6.
The liquid crystal display panel 2 includes a pixel matrix composed of a plurality of sub-pixels defined at each intersection of the gate lines and the data lines. Each of the sub-pixels includes a liquid crystal cell Clc for controlling light transmittance in accordance with the pixel signal and a thin film transistor (TFT) for driving the liquid crystal cell Clc.
The TFT is turned-on when a scan signal DL to the liquid crystal cell Clc. Herein, the scan signal is a gate high voltage VGH from the gate line GL provided to the TFT to supply the pixel signal from the data line Further. Conversely, the TFT is turned off when a gate low voltage VGL is supplied thereto to maintain the pixel signal charged to the liquid crystal cell Clc.
The liquid crystal cell Clc can be equivalently represented as a capacitor, and includes a common electrode and a pixel electrode connected to the TFT where a liquid crystal material is inserted between the common electrode and the pixel electrode. The liquid crystal cell Clc further comprises a storage capacitor Cst for stably maintaining the pixel signal charged thereto until the next pixel signal is charged. Such a liquid crystal cell Clc varies with an arrangement of the liquid crystal having a dielectric anisotropy in accordance with the pixel signal charged through the TFT, and the liquid crystal cell Clc represents gray levels by controlling the light transmittance.
The gate driver 4 shifts a gate start pulse (hereinafter, referred to as. “GSP”) from a timing controller 8 in accordance with a gate shift clock (hereinafter, referred to as “GSC) to supply a scan pulse of the gate high voltage VGH to the gate lines GL1 to GLm. The gate driver 4 supplies a gate low voltage VGL during a scan pulse of the gate high voltage VGH is not supplied to the gate lines GL1 to GLm. Further, the gate driver 4 controls a width of the scan pulse in accordance with a gate output enable (hereinafter, referred to as “GOE”) from the timing controller 8. Such a gate driver 4 comprises a plurality of gate driving ICs for driving the gate lines GL0 to DLn in a time-divided manner.
The data driver 6 shifts a source start pulse (hereinafter, referred to as “SSP”) from the timing controller 8 in accordance with a source shift clock (hereinafter, referred to as “SSC) to generate a sampling signal. Further, the data driver 6 latches input pixel data RGB by the SSC in accordance with the sampling signal, and then supplies the latched pixel data by a horizontal line unit in response to a source output enable (hereinafter referred to as “SOE”) signal. Then, the data driver 6 converts the pixel data RGB supplied on horizontal line basis into analog pixel signals by using reference gamma voltages from the reference gamma voltage part 10 to supply the analog pixel signals to the data lines DL1 to DLm. At this time, the data driver 6 determines the polarity of the pixel signal, in response to the polarity controlling signal (hereinafter, referred to as “POL”) from the timing controller 8 at the time of the conversion of the pixel data into the analog pixel signal. Further, the data driver 6 determines the timing that the analog pixel signals are supplied to the data lines DL1 to DLm in response to the SOE signal. The data driver 6 includes a plurality of the data driver ICs for driving the data lines DL1 to DLm in a time-divided manner.
The timing controller 8 generates GSP, GSC and GOE signals for controlling the gate driver 4, and generates SSP, SSC, SOE and POL signals for controlling the data driver 6. In this case, the timing controller 8 generates a data enable DE signal representing an effective data period, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, and a variety of control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, and POL by using a dot clock DCLK to determine the transmission timing of the pixel data RGB.
FIG. 2 is a block diagram showing a data driver IC included in the data driver 6 of FIG. 1.
A data driver IC 12 shown in the FIG. 2 includes a shift register 18 for sequentially generating a sampling signal, a latch part 20 for latching pixel data in response to the sampling signal, a digital-analog convert part 22 (hereinafter, referred to as “DAC”) for converting the pixel data latched in the latch part 20 into the analog pixel signals, and an output buffering part 30 for buffering the analog pixel signals from the DAC part 22. Further, the data driver IC 12 includes a signal controller 14 for relaying the pixel data and control signals such as SSC, SSP, SOE, and POL signals supplied from the timing controller 8, and a gamma voltage part 16 for supplying a reference gamma voltages for the DAC part 22. The data driving IC 12 drives k-number of the data lines DL1 to DLk among m-number of the data lines DL1 to DLm as shown in FIG. 1.
The signal controller 14 relays the control signals such as SSP, SSC, SOE, and POL signals from the timing controller 8 and the pixel data to be supplied to corresponding components.
The gamma voltage part 16 subdivides a plurality of the reference gamma voltages inputted from the reference gamma voltage part 10 by gray levels to supply the reference gamma voltages to the DAC part 22. In this case, the gamma voltage part 16 generates a set of polarity gamma voltages and a set of negative gamma voltages with respect to the common voltage, which is the reference signal in driving liquid crystal cell Clc.
The shift register 18 sequentially shifts the SSP from the signal controller 14 in accordance with the SSC to generate the sampling signal.
The latch part 20, in response to the sampling signal from the shift register 18, samples and latches sequentially the pixel data from the signal controller 14. The latch part 20 is comprised of k-number of latches for latching k-number of pixel data. Each of the latches has a size corresponding to the bit number, e.g., 3-bit or 6-bit, of the pixel data. The latch part 20 simultaneously outputs the latched k-number of pixel data in response to the SOE signal from the signal controller 14. The latch part 20 includes a first latch part (not shown) for sampling and latching the pixel data inputted thereto and a second latch part (not shown) for simultaneously supplying the latched pixel data in the first latch part in response to the SOE signal.
The DAC part 22 converts the pixel data from the latch part 20 into the analog pixel signals having positive and negative polarities. To this end, the DAC part 22 includes the k-number of the DACs 21. Each of the DACs 21 includes a PDAC, a NDAC and a multiplexer (hereinafter referred to as “MUX”) 28 for selectively outputting output signals of the PDAC and the NDAC.
The PDAC functions to convert the digital pixel data inputted from the latch part 20 into the positive analog pixel signal using the positive gamma voltage from the gamma voltage part 16.
The NDAC functions to convert the digital pixel data inputted from the latch part 20 into the negative analog pixel signal using the negative gamma voltage from the gamma voltage part 16.
In response to the POL signal from the signal controller 14, the MUX28 selects one of the positive pixel signal from the PDAC and the negative pixel signal from the NDAC.
The output buffering part 32 includes the k-number of output buffers 32. Each of the output buffers 32 includes a voltage follower connected in series to each of the data lines DL1 to DLk. Each output buffers 32 is to buffer the pixel signals from the DAC part 22 and output the pixel signals to the data lines DL1 to DLk.
As set forth above, the data driving IC 12 of the related art requires the k-number of the DACs 22 having the PDAC, the NDAC, and the MUX28 in order to drive the k-number of the data lines DL1 to DLk. In other words, the related art data driving IC 12 requires the k-number of the PDAC and the NDAC for driving the k-number of data lines DL1 to DLk. Therefore, the related art data driving IC 12 has the complicated constitution and its manufacturing cost is high as much as about 20-30% of the total manufacturing cost of the liquid crystal display module. Accordingly, there is a need to reduce the number of the driving Ics, thereby saving the manufacturing costs.
To do this, there has been a measure for reducing the number of the driving ICs by simply incorporating the data driving ICs. However, this measure makes the IC's size larger, so that the area of a tape carrier package (hereinafter referred to as a “TCP”) or a chip on film (hereinafter referred to as a “COF”) on which the driving is IC mounted becomes increased. Accordingly, the enlarged area of the TCP or the COF increases the manufacturing cost and provides a poor yield.
Furthermore, in the case of simplifying the constitution of the data driving IC to reduce the number of the driving ICs, it should meet the additional requirement to prevent a distortion of the pixel signal that affects the display quality.